1. Field of the Invention
The present invention relates to a data processor for changing the arrangement order of a byte data so that the data can be transferred between internal and external memory devices of the processor at high speed.
2. Description of the Prior Art
A microprocessor is connected to an external memory via an external bus. To implement interface between the external bus and an internal bus of the microprocessor, a data processor is necessary for the microprocessor. In the case of a 32-bit microprocessor, for instance, 4-byte memory operand data are transferred between the external memory and the data processor. These data are usually transferred for each byte unit. In data transfer operation, the least significant bit (LSB) of the data must match the LSB of the data transferred to the internal bus, internal registers and external bus.
In the prior-art data processor, when the arrangement order of data stored in the external memory is different from that of data to be processed within the microprocessor, since the data arrangement is changed in accordance with software stored within the data processor incorporated in the microprocessor, there exist problems in that the data arrangement changing time is required and therefore the access time increases or the processing speed decreases, and additionally the capacity of the memory device increases.
The configuration of the prior-art data processor will be described in further detail hereinafter with reference to FIGS. 1 to 3, under DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT.